View 88CO196EC_1204015.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller
Datasheet
Product Features
* * * * * * * * * * * * * * * *
256 Kbytes on-chip flash program memory 40 MHz operation Optional clock quadrupler Programmable clock output signal (CLKOUT) 2 Mbytes of linear address space 1.25 Kbytes of register RAM 2.75 Kbytes of code RAM Register-to-register architecture Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits Two peripheral interrupt handlers (PIHs) provide direct hardware handling of up to 45 interrupts Up to 59 I/O port pins Full-duplex serial port with dedicated baud-rate generator Enhanced synchronous serial I/O unit (SSIO) 16 10-bit A/D channels with auto-scan mode and dedicated results registers Controller area network (CAN) 2.0 networking protocol Serial debug unit provides read and write access to code RAM with no CPU overhead
*
Chip-select unit (CSU) -- Three chip-select pins -- Dynamic demultiplexed/multiplexed address/data bus for each chip-select -- Programmable wait states (0, 1, 2, or 3) for each chip-select -- Programmable bus width (8- or 16-bit) for each chip-select -- Programmable address range for each chip-select
*
Event processor array (EPA) -- Two flexible 16-bit timer/counters -- Five high-speed capture/compare channels with a lock feature for noise filtering -- 10 enhanced high-speed capture/compare channels with period and duty cycle measurement capability, as well as a lock feature for noise filtering
* *
Complete system development support Packaging -- 132-pin PQFP
* Temperature Offerings
-- Commercial (0C - 70C) -- Extended (-40C - 85C)
The Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller is the first member of the MCS(R)96 family of microcontrollers to integrate flash memory on-chip. The Intel(R) 88CO196EC, with its integrated flash memory, brings a new level of integration that offers embedded system designers cost-effective solutions.
Order Number: 273970-002 August, 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) February, 2004, Intel Corporation
Intel(R) 88CO196EC
Contents
1.0 Product Overview ............................................................................................................... 7 1.1 2.0 3.0 4.0 5.0 Nomenclature Overview ........................................................................................ 8 Pinout ................................................................................................................................. 9 Signals.............................................................................................................................. 11 Address Map ....................................................................................................................21 Electrical Characteristics .................................................................................................. 23 5.1 6.0 DC Characteristics .............................................................................................. 23
Explanation of AC Symbols.............................................................................................. 25 6.1 6.2 6.3 6.4 6.5 6.6 6.7 AC Characteristics -- Multiplexed Bus Mode...................................................... 26 AC Characteristics -- Demultiplexed Bus Mode ................................................. 30 Deferred Bus Timing Mode ................................................................................. 34 AC Characteristics -- Serial Port, Mode 0 .......................................................... 35 AC Characteristics -- Synchronous Serial Port .................................................. 36 AC Characteristics -- Serial Debug Unit............................................................. 37 A/D Sample and Conversion Times .................................................................... 38 6.7.1 AC Characteristics -- A/D Converter, 10-Bit Mode ................................ 39 6.7.2 AC Characteristics -- A/D Converter, 8-Bit Mode .................................. 40 External Clock Drive ............................................................................................41 Test Output Waveforms ...................................................................................... 42 Flash Memory Erase Performance...................................................................... 42
6.8 6.9 6.10 7.0
Thermal Characteristics ................................................................................................... 43
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller Block Diagram ...................... 7 Product Nomenclature........................................................................................... 8 Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package........ 9 System Bus Timing Diagram (Multiplexed Bus Mode) ........................................28 READY Timing Diagram (Multiplexed Bus Mode) ...............................................29 System Bus Timing Diagram (Demultiplexed Bus Mode) ................................... 32 READY Timing Diagram (Demultiplexed Bus Mode) .......................................... 33 Deferred Bus Mode Timing Diagram................................................................... 34 Serial Port Waveform -- Mode............................................................................ 35 Synchronous Serial Port...................................................................................... 36 Serial Debug Unit ................................................................................................ 37 External Clock Drive Waveforms.........................................................................41 AC Testing Output Waveforms............................................................................ 42 Float Waveforms During 5.0 Volt Testing............................................................ 42
3
Intel(R) 88CO196EC
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Description of Product Nomenclature ................................................................... 8 Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package Pin Assignments .......................................................... 10 Signal Descriptions ............................................................................................. 11 Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller Address Map....................... 21 DC Characteristics at Vcc = 4.75 V - 5.25 V ....................................................... 23 AC Timing Symbol Definitions............................................................................. 25 AC Characteristics, Multiplexed Bus Mode ......................................................... 26 AC Characteristics, Demultiplexed Bus Mode .................................................... 30 Serial Port Timing -- Mode 0............................................................................. 35 Synchronous Serial Port Timing.......................................................................... 36 Serial Debug Unit Timing .................................................................................... 37 10-bit A/D Operating Conditions ......................................................................... 39 10-Bit Mode A/D Characteristics Over Specified Operating Conditions.............. 39 8-Bit A/D Operating Conditions ........................................................................... 40 8-Bit Mode A/D Characteristics Over Specified Operating Conditions................ 40 External Clock Drive............................................................................................ 41 Flash Memory Erase Performance ..................................................................... 42 Thermal Characteristics ...................................................................................... 43
4
Intel(R) 88CO196EC
Revision History
Date February 2004 August 2004 Revision 001 002 Initial release To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". Description
5
Intel(R) 88CO196EC
6
Intel(R) 88CO196EC
1.0
Figure 1.
Product Overview
Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller Block Diagram
Port 9 Port 6 Port 3,4,5
Watchdog Timer
Stack Overflow Module
A/D Converter
CAN
SSIO0 SSIO1
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
SIO
Baud-rate Generator
Bus Control A20:16 A15:0 AD15:0
Memory Data Bus (16)
Memory Addr Bus (24)
Bus Controller
Chip-select Unit
Port 2
Peripheral Interrupt Handler Peripheral Transaction Server Interrupt Controller EPA Ports 7,8
Bus-Control Interface Unit Queue Microcode Engine
5 Capture/ Compares 2 Timers 10 Enhanced Capture/ Compares
Source (16)
ALU
Register RAM 1.25 Kbytes
Memory Interface Unit
Destination (16)
Code/Data RAM 2.75 Kbytes
Serial Debug Unit
Flash 256 Kbytes A4324-01
The Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller is highly integrated with an enhanced peripheral set. The integrated CAN 2.0 networking protocol provides for efficient communication to a high-speed CAN bus. The serial debug unit (SDU) provides system debug and development capabilities. The SDU can set a single hardware breakpoint. In addition, the SDU provides read and write access to code RAM through a high-speed, dedicated serial link. A stack overflow/underflow monitor assists in code development by causing a nonmaskable interrupt if the stack pointer crosses a user-defined boundary. The 16-channel A/D converter supports an auto-scan mode that operates with no CPU overhead. Each A/D channel has a dedicated result register. The EPA supports high-speed event captures and output compares with 15 programmable, high-speed channels.
Datasheet
7
Intel(R) 88CO196EC
1.1
Figure 2.
Nomenclature Overview
Product Nomenclature
XX
Te e mp tu ra re
8
X
Pr og
X
Pr oc
X
Pr
XXXXX
Pr od
X
ep St
od
es sI mo ry
e yp on tT ati uc
ily am tF uc
ra m
p in de gI
Me
nfo Op
rm tio
nti r fie
ns
B3165-01
Table 1.
Description of Product Nomenclature
Parameter Temperature Options Program-Memory Process Information Product Type Product Family Device Speed Options x x x C O 196EC no mark 40 MHz Description Commercial temperature range (0 C to 70 C case) Extended temperature range (-40 C to 85 C case) Internal flash memory CHMOS Standard Embedded Product
8
Datasheet
Intel(R) 88CO196EC
2.0
Figure 3.
Pinout
Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package
ACH7 ACH8 ACH9 ANGND VREF VSS ACH10 ACH11 ACH12 ACH13 ACH14 ACH15 VSS VCC P8.0 / EPAPWM8 / BLK0# P8.1 / EPAPWM9 / BLK1# P8.2 / EPA10 / T1CLK / BLK2# P8.3 / EPA11 / T1RST / BLK3# P8.4 / EPA12 / T2CLK P8.5 / EPA13 / T2RST P8.6 / EPA14 P8.7 VCC VSS P7.0 / EPAPWM0 P7.1 / EPAPWM1 P7.2 / EPAPWM2 P7.3 / EPAPWM3 P7.4 / EPAPWM4 P7.5 / EPAPWM5 P7.6 / EPAPWM6 P7.7 / EPAPWM7
VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
ACH6 ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 VCC VSS P2.0 / TXD P2.1 / RXD / PALE# P2.2 / EXTINT / PROG# P2.3 P2.4 / AINC# P2.5 P2.6 / HOLD# / CPVER / ONCE# / HLDA# P2.7 / CLKOUT / PACT# VSS VCC TXCAN RXCAN P9.2 / SC0 P9.3 / SD0 P9.4 / SC1 / CHS# P9.5 / SD1 P9.6 P9.7 NMI RESET# EA# P3.0 / AD0 / PBUS0 P3.1 / AD1 / PBUS1 P3.2 / AD2 / PBUS2
88CO196EC
View of component as mounted on PC board.
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
P3.3 / AD3 / PBUS3 P3.4 / AD4 / PBUS4 P3.5 / AD5 / PBUS5 P3.6 / AD6 / PBUS6 P3.7 / AD7 / PBUS7 P4.0 / AD8 / PBUS8 P4.1 / AD9 / PBUS9 P4.2 / AD10 / PBUS10 P4.3 / AD11 / PBUS11 P4.4 / AD12 / PBUS12 P4.5 / AD13 / PBUS13 P4.6 / AD14 / PBUS14 P4.7 / AD15 / PBUS15 CRBUSY# CROUT CRDCLK VSS VPP CRIN VSS VSS VSS PLLEN VSS VCC A7 A6 A5 A4 A3 A2 A1 A0
A15 A14 A13 A12 VCC VSS A11 P6.0 / A16 / PBUS16 P6.1 / A17/ PBUS17 P6.2 / A18/ PBUS18 P6.3 / A19/ PBUS19 P6.4 / A20/ PBUS20 P6.5 / CS0# / PMODE0 P6.6 / CS1#/ PMODE1 P6.7 / CS2#/ PMODE2 VSS VCC P5.0 / ALE / ADV# P5.1 / INST P5.2 / WR# / WRL# P5.3 / RD# P5.4 / BREQ# / TMODE0# VSSPLL VCCPLL XTAL2 XTAL1 VCC P5.5 / BHE# / WRH# / TMODE1# P5.6 / READY P5.7 / RPD A10 A9 A8
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
B3055-01
Datasheet
9
Intel(R) 88CO196EC
Table 2.
Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller 132-Pin PQFP Package Pin Assignments
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 ACH7 ACH8 ACH9 ANGND VREF VCC VSS ACH10 ACH11 ACH12 ACH13 ACH14 ACH15 VSS VCC P8.0/EPAPWM8/BLK0# P8.1/EPAPWM9/BLK1# P8.2/EPA10/T1CLK/BLK2# P8.3/EPA11/T1RST/BLK3# P8.4/EPA12/T2CLK P8.5/EPA13/T2RST P8.6/EPA14 P8.7 VCC VSS P7.0/EPAPWM0 P7.1/EPAPWM1 P7.2/EPAPWM2 P7.3/EPAPWM3 P7.4/EPAPWM4 P7.5/EPAPWM5 P7.6/EPAPWM6 P7.7/EPAPWM7 A15 A14 A13 A12 VCC VSS A11 P6.0/A16/PBUS16 P6.1/A17/PBUS17 P6.2/A18/PBUS18 P6.3/A19/PBUS19
Name
Pin
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Name
P6.4/A20/PBUS20 P6.5/CS0#/PMODE0 P6.6/CS1#/PMODE1 P6.7/CS2#/PMODE2 VSS VCC P5.0/ALE/ADV# P5.1/INST P5.2/WR#/WRL# P5.3/RD# P5.4/BREQ#/TMODE0# VSSPLL VCCPLL XTAL2 XTAL1 VCC P5.5/BHE#/WRH#/TMODE1# P5.6/READY P5.7/RPD A10 A9 A8 A0 A1 A2 A3 A4 A5 A6 A7 VCC VSS PLLEN VSS VSS VSS CRIN VPP VSS CRDCLK CROUT CRBUSY# P4.7/AD15/PBUS15 P4.6/AD14/PBUS14
Pin
89 90 91 92 93 94 95 96 97 98 99
Name
P4.5/AD13/PBUS13 P4.4/AD12/PBUS12 P4.3/AD11/PBUS11 P4.2/AD10/PBUS10 P4.1/AD9/PBUS9 P4.0/AD8/PBUS8 P3.7/AD7/PBUS7 P3.6/AD6/PBUS6 P3.5/AD5/PBUS5 P3.4/AD4/PBUS4 P3.3/AD3/PBUS3
100 P3.2/AD2/PBUS2 101 P3.1/AD1/PBUS1 102 P3.0/AD0/PBUS0 103 EA# 104 RESET# 105 NMI 106 P9.7 107 P9.6 108 P9.5/SD1 109 P9.4/SC1/CHS# 110 P9.3/SD0 111 P9.2/SC0 112 RXCAN 113 TXCAN 114 VCC 115 VSS 116 P2.7/CLKOUT/PACT# 117 P2.6/HLDA#/ONCE#/CPVER 118 P2.5 HOLD# 119 P2.4/AINC# 120 P2.3 121 P2.2/EXTINT/PROG# 122 P2.1/RXD/PALE# 123 P2.0/TXD 124 VSS 125 VCC 126 ACH0 127 ACH1 128 ACH2 129 ACH3 130 ACH4 131 ACH5 132 ACH6
10
Datasheet
Intel(R) 88CO196EC
3.0
Table 3.
Signals
Signal Descriptions (Sheet 1 of 9)
Name Type System Address Bus A15:0 O These address pins provide address bits 0-15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. Address Pins 16-20 These address pins provide address bits 16-20 during the entire external memory cycle during both multiplexed and demultiplexed bus modes, supporting extended addressing of the 2-Mbyte address space. NOTE: Internally, there are 24 address bits; however, only 21 external address pins (A20:0) are implemented. The internal address space is 16 Mbytes (000000-FFFFFFH) and the external address space is 2 Mbytes (000000-1FFFFFH). The microcontroller resets to FF2080H in internal memory or 1F2080H in external memory. A20:16 share package pins with P6.4:0 and PBUS20:16. Analog Channels ACH15:0 I These signals are analog inputs to the A/D converter. The ANGND and VREF pins must be connected for the A/D converter to function. Address/Data Lines The function of these pins depends on the bus width and mode. 16-bit Multiplexed Bus Mode: AD15:0 drive address bits 0-15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit Multiplexed Bus Mode: AD15:0 I/O AD15:8 drive address bits 8-15 during the entire bus cycle. AD7:0 drive address bits 0-7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit Demultiplexed Mode: AD15:0 drive or receive data during the entire bus cycle. 8-bit Demultiplexed Mode: AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that is currently on the high byte of the internal bus. AD15:8 share package pins with P4.7:0. AD7:0 share package pins with P3.7:0. Address Valid This active-low output signal is asserted only during external memory accesses. ADV# indicates that valid address information is available on the system address/data bus. The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes. An external latch can use this signal to demultiplex the address from the address/data bus. A decoder can also use this signal to generate chip selects for external memory. ADV# shares a package pin with P5.0 and ALE. Auto Increment During slave programming, this active-low input enables the auto-increment feature. (Auto increment allows reading or writing of sequential flash memory locations, without requiring address transactions across the programming bus for each read or write.) AINC# is sampled after each location is programmed or dumped. If AINC# is asserted, the address is incremented and the next data word is programmed or dumped. AINC# shares a package pin with P2.4. Description
A20:16
O
ADV#
O
AINC#
I
Datasheet
11
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 2 of 9)
Name Type Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus. An external latch can use this signal to demultiplex address bits 0-15 from the address/data bus in multiplexed mode. ALE shares a package pin with P5.0 and ADV#. Analog Ground ANGND GND ANGND must be connected for A/D converter operation. ANGND and VSS should be nominally at the same potential. Byte High Enable During 16-bit bus cycles, this active-low output signal is asserted for word and high-byte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed address/data bus), to determine which memory byte is being transferred over the system bus: BHE# O BHE# 0 0 1 AD0 or A0 0 1 0 Byte(s) Accessed both bytes high byte only low byte only Description
ALE
O
BHE# shares a package pin with P5.5, TMODE1# and WRH#. When this pin is configured as a special-function signal (P5_MODE.5 = 1), the chip configuration register 0 (CCR0) determines whether it functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#. Block x Active. When active, these signals indicate that programming of data is occurring within the corresponding flash memory address range or that the corresponding physical block is being erased. The address range and physical block associated with the BLKx# signals are as follows: BLK3:0# O BLK0# BLK1# BLK2# BLK3# Address Range FC0000-FCFFFFH FD0000-FDFFFFH FE0000-FEFFFFH FF0000-FFFFFFH Physical Block even bytes at FC0000-FDFFFEH odd bytes at FC0001-FDFFFFH even bytes at FE0000-FFFFFEH odd bytes at FE0001-FFFFFFH
During test-ROM execution mode, the contents of pages FFH and FBH are swapped. BLK1:0# shares a package pin with P8.1:0 and EPAPWM9:8. BLK2# shares a package pin with P8.2, EPA10, and T1CLK. BLK3# shares a package pin with P8.3, EPA11, and T1RST. Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. When the bus-hold protocol is enabled (WSR.7 is set), the P5.4/BREQ# pin can function only as BREQ#, regardless of the configuration selected through the port configuration registers (P5_MODE, P5_DIR, and P5_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). The microcontroller can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted. BREQ# shares a package pin with P5.4 and TMODE0#. Clock Output CLKOUT O Output of the internal clock generator. You can select one of four frequencies: f/2, f/4, f/8, or f/16. CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7 and PACT#.
BREQ#
O
12
Datasheet
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 3 of 9)
Name Type Cumulative Program Verification CPVER O During slave or UPROM programming, a high signal indicates that the program operation was successful, while a low signal indicates that an error occurred during the program operation. CPVER shares a package pin with P2.6, HLDA#, and ONCE#. Code RAM Busy CRBUSY# O When active, this signal indicates that the serial debug unit (SDU) is busy processing a code RAM command. No data can be transferred during this time. Code RAM Clock CRDCLK I Provides the clock signal for the serial debug unit (SDU). The maximum clock frequency equals one-half the operating frequency (f/2). Code RAM Data Input CRIN I Serial input for test instructions and data into the serial debug unit (SDU). Data is transferred in 8-bit bytes with the most-significant bit (MSB) first. Each byte is sampled on the rising edge of CRDCLK. Code RAM Data Output CROUT O Serial output for data from the serial debug unit (SDU). Data is transferred in 8-bit bytes with the most-significant bit (MSB) first. Each byte is valid on the rising edge of CRDCLK. Chip-select Lines 0-2 The active-low output CSx# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x. If the external memory address is outside the range assigned to the three chip selects, no chip-select output is asserted and the bus configuration defaults to the CS2# values. Immediately following reset, CS0# is automatically assigned to the range (1F2000-1F20FFH if external). CS2:0# share package pins with P6.7:5 and PMODE2:0. External Access This input determines whether memory accesses to flash program memory partitions (FC0000-FFFFFFH) are directed to internal or external memory. These accesses are directed to internal flash memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# is sampled and latched only on the rising edge of RESET#. Changing the level of EA# after reset has no effect. Always connect EA# to VSS when using a microcontroller that has no internal nonvolatile memory or V CC when using the internal flash memory. Event Processor Array (EPA) Capture/Compare Channels EPA14:10 I/O High-speed input/output signals for the EPA capture/compare channels. EPA14:10 share package pins with the following signals: EPA10/P8.2/T1CLK/BLK2#, EPA11/P8.3/T1RST/BLK3#, EPA12/P8.4/T2CLK, EPA13/P8.5/T2RST, EPA14/P8.6. Event Processor Array (EPA) PWM Receiver/Transmitter Channels EPAPWM9:0 I/O High-speed input/output signals for the enhanced EPA PWM receiver/transmitter channels. EPAPWM9:8 share package pins with P8.1:0 and BLK1:0#. EPAPWM7:0 share package pins with P7.7:0. Description
CS2:0#
O
EA#
I
Datasheet
13
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 4 of 9)
Name Type External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high time is one state time. In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation. The interrupt does not need to be enabled, but the pin must be configured as a special-function input. If the EXTINT interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT shares a package pin with P2.2 and PROG#. Bus Hold Acknowledge The HLDA# pin is used in systems with more than one processor using the system bus. The microcontroller asserts HLDA# to indicate that it has released the bus in response to HOLD# and another processor can take control. (This signal is active low to avoid misinterpretation by external hardware immediately after reset.) When the bus-hold protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). Bus Hold Request An external device uses this active-low input signal to request control of the bus. When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can function only as HOLD#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). If P2.5 is configured as a general-purpose I/O signal, the device does not recognize signals on this pin as HOLD#. Instead, the bus controller receives an internal HOLD signal. This enables the device to access the external bus while it is performing I/O at P2.5. Instruction Fetch INST O When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. INST shares a package pin with P5.1. Nonmaskable Interrupt NMI I In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized. On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the microcontroller into on-circuit emulation (ONCE) mode. This mode puts all pins into a high-impedance state, thereby isolating the microcontroller from other components in the system. The value of ONCE# is latched when the RESET# pin goes inactive. While the microcontroller is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the microcontroller by pulling the RESET# signal low. To prevent inadvertent entry into ONCE mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the VIH specification. ONCE# shares a package pin with P2.6, TMODE1#, and CPVER. Description
EXTINT
I
HLDA#
O
HOLD#
I
ONCE#
I
14
Datasheet
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 5 of 9)
Name Type Port 2 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. P2.7:0 I/O P2.6 is multiplexed with the ONCE function. If you choose to configure this pin as an input, always hold it high during reset and ensure that your system meets the VIH specification to prevent inadvertent entry into ONCE mode. Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD/PALE#, P2.2/EXTINT/PROG#, P2.4/AINC#, P2.5 HOLD# P2.6/ONCE#/CPVER, HLDA#, and P2.7/CLKOUT/PACT#. P2.3 is a dedicated general-purpose I/O signal. Port 3 P3.7:0 I/O This is a memory-mapped, 8-bit, bidirectional port with programmable open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0 and PBUS7:0. Port 4 P4.7:0 I/O This is a memory-mapped, 8-bit, bidirectional port with programmable open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8 and PBUS15:8. Port 5 This is a memory-mapped, 8-bit, bidirectional port that shares package pins with individually selectable control signals. P5.4 shares a package pin with TMODE0#. If this pin is held low during reset, the device will enter a test mode. To prevent inadvertent entry into a reserved test mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the VIH specification. Port 5 shares package pins with the following signals: P5.0/ALE/ADV#, P5.1/INST, P5.2/WR#/WRL#, P5.3/RD#, P5.4/BREQ#/TMODE0#, P5.5/BHE#/WRH#, P5.6/READY, and P5.7/RPD. Port 6 P6.7:0 O This is a standard, 8-bit, bidirectional port individually selectable special-function signals. Port 6 shares package pins with the following signals: P6.0/A16/PBUS16, P6.1/A17/PBUS17, P6.2/A18/PBUS18, P6.3/A19/PBUS19, P6.4/A20/PBUS20, P6.5/CS0#/PMODE0, P6.6/CS1#/PMODE1, and P6.7/CS2#/PMODE2. Port 7 P7.7:0 I/O This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. P7.7:0 share package pins with EPAPWM7:0. Port 8 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. P8.7:0 I/O Port 8 shares package pins with the following signals: P8.0/EPAPWM8/BLK0#, P8.1/EPAPWM9/BLK1#, P8.2/EPA10/T1CLK/BLK2#, P8.3/EPA11/T1RST/BLK3#, P8.4/EPA12/T2CLK, P8.5/EPA13/T2RST, P8.6/EPA14. P8.7 is a dedicated general-purpose I/O signal. Description
P5.7:0
I/O
Datasheet
15
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 6 of 9)
Name Type Port 9 P9.7:2 I/O This is a standard, 6-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 9 shares package pins with the following signals: P9.2/SC0, P9.3/SD0, P9.4/SC1, and P9.5/SD1. P9.6 and P9.7 are dedicated general-purpose I/O signals. O PACT# Programming Active During slave or UPROM programming, a low signal indicates that programming is in progress, while a high signal indicates that the operation is complete. PACT# shares a package pin with P2.7 and CLKOUT. Programming ALE PALE# I During slave or UPROM programming, a falling edge causes the microcontroller to read the programming bus. PALE# is multiplexed with P2.1 and RXD. Address/Command/Data Bus PBUS20:0 I/O Address and data input/output bus during slave and UPROM programming. PBUS20:16 share package pins with A20:16 and P6.4:0; PBUS15:8 share package pins with AD15:8 and P4.7:0; PBUS7:0 share package pins with AD7:0 and P3.7:0. Phase-locked Loop Enable PLLEN I This active-high input pin enables the on-chip clock multiplier. This pin should be tied to VCC to activate the PLL or V SS to disable the PLL. The state of the PLL can only be changed at the time of reset. Programming Mode Select PMODE2:0 I These pins, along with the TMODE1:0# pins, determine the programming mode. PMODE2:0 are sampled after a device reset and must be static while the microcontroller is operating. PMODE2:0 share package pins with P6.7:5 and CS2:0#. Programming Start During programming, a falling edge latches data on the programming bus and begins programming, while a rising edge ends programming. The current location is programmed with the same data as long as PROG# remains asserted, so the data on the programming bus must remain stable while PROG# is active. During a word dump, a falling edge causes the contents of a flash memory location to be output on the PBUS, while a rising edge ends the data transfer. PROG# shares a package pin with P2.2 and EXTINT. Read RD# O Read-signal output to external memory. RD# is asserted only during external memory reads. RD# shares a package pin with P5.3. Ready Input This active-high input can be used to insert wait states in addition to those programmed in the chip configuration byte 0 (CCB0) and the bus control x register (BUSCONx). CCB0 is programmed with the minimum number of wait states (0-3) for an external fetch of CCB1, and BUSCONx is programmed with the minimum number of wait states (0-3) for all external accesses to the address range assigned to the chip-select x channel. If READY is low when the programmed number of wait states is reached, additional wait states are added until READY is pulled high. READY shares a package pin with P5.6. Description
PROG#
I
READY
I
16
Datasheet
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 7 of 9)
Name Type Reset A level-sensitive reset input to, and an open-drain system reset output from, the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the microcontroller to reset and return to normal operating mode. After a reset, the first instruction fetch is from FF2080H (or 1F2080H in external memory). Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor between RPD and VSS if either of the following conditions are true. * The internal oscillator is the clock source * The phase-locked loop (PLL) circuitry is enabled (see PLLEN signal description) RPD I The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. Refer to the "Special Operating Modes" chapter of the for details on selecting the capacitor. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true. * An external clock input is the clock source * The phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. RPD shares a package pin with P5.7. Receive CAN Message RXCAN I This signal carries messages from other nodes on the CAN bus to the integrated CAN controller. Receive Serial Data RXD I/O In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1 and PALE#. Clock Pins for SSIO0 and 1 SC1:0 I/O In standard mode, SC0 is the serial clock pin for channel 0 and SC1 is the serial clock pin for channel 1. In duplex and channel-select modes, SC0 is the serial clock pin for both channels 0 and 1 and SC1 is not available. SC0 shares a package pin with P9.2, and SC1 shares a package pin with P9.4. Data Pins for SSIO0 and 1 SD1:0 I/O These pins are the data I/O pins for SSIO0 and 1. For transmissions, configure SDx as a complementary output signal. For receptions, configure SDx as a high-impedance input signal. SD0 shares a package pin with P9.3, and SD1 shares a package pin with P9.5. Timer 1 External Clock T1CLK I External clock for timer 1. Timer 1 is programmable to increment or decrement on the rising edge, the falling edge, or both rising and falling edges of T1CLK. T1CLK shares a package pin with P8.2, EPA10, and BLK2#. Timer 2 External Clock T2CLK I External clock for timer 2. Timer 2 is programmable to increment or decrement on the rising edge, the falling edge, or both rising and falling edges of T2CLK. and External clock for the serial I/O baud-rate generator input (program selectable). T2CLK shares a package pin with P8.4 and EPA12. Description
RESET#
I/O
Datasheet
17
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 8 of 9)
Name Type Timer 1 External Reset T1RST I External reset for timer 1. Timer 1 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of T1RST. T1RST shares a package pin with P8.3, EPA11, and BLK3#. Timer 2 External Reset T2RST I External reset for timer 2. Timer 2 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of T2RST. T2RST shares a package pin with P8.5 and EPA13. TMODE1:0# Test-Mode Entry If these pins are held low during reset, the microcontroller will enter a test mode. The value of several other pins defines the actual test mode. All test modes, except TROM execution, are reserved for Intel factory use. If you choose to configure these signals as inputs, always hold them high during reset and ensure that your system meets the VIH specification to prevent inadvertent entry into test mode. TMODE0# shares a package pin with P5.4 and BREQ#; TMODE1# shares a package pin with P5.5, BHE#, WRH#. Transmit CAN Message TXCAN O This signal carries messages from the integrated CAN controller to other nodes on the CAN bus. Transmit Serial Data TXD O In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0. VCC PWR Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Digital Supply Voltage for the Phase-locked Loop (PLL) Circuitry VCCPLL PWR Connect this pin to the digital supply voltage. VCCPLL and VCC should be nominally at the same voltage. Programming Voltage VPP PWR During Flash Program/Erase, the VPP pin is typically at +12 V (VPP voltage). During normal operation the VPP pin is tied to VSS. VREF PWR Reference Voltage for the A/D Converter This pin supplies operating voltage to the A/D converter. Digital Circuit Ground VSS GND These pins supply ground for the digital circuitry. Connect each VSS pin to ground through the lowest possible impedance path. Digital Circuit Ground for the Phase-locked Loop (PLL) Circuitry VSSPLL GND Connect this pin to ground through the lowest possible impedance path. VSSPLL and VSS should be nominally at the same potential. Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# O WR# shares a package pin with P5.2 and WRL#.
Description
I
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
18
Datasheet
Intel(R) 88CO196EC
Table 3.
Signal Descriptions (Sheet 9 of 9)
Name Type Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. WRH# shares a package pin with P5.5 and BHE#. When this pin is configured as a special-function signal (P5_MODE.5 = 1), the chip configuration register 0 (CCR0) determines whether it functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#. Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares a package pin with P5.2 and WR#.
Description
WRH#
O
WRL#
O
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.
XTAL1
I
Inverted Output for the Crystal/Resonator XTAL2 O Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
Datasheet
19
Intel(R) 88CO196EC
20
Datasheet
Intel(R) 88CO196EC
4.0
Table 4.
Address Map
Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller Address Map (Sheet 1 of 2)
Hex Address FFFFFF FF2140 FF213F FF20C0 FF20BF FF2080 FF207F FF2000 FF1FFF FC0000 FBFFFF FB0000 FAFFFF E10000 E0FFFF 010000 00FFFF 002000 001FFF 001FE0 001FDF 001E00 001DFF 001D00 001CFF 001C00 001BFF 000F00 Description Addressing Modes for Data Accesses Extended Extended Extended Extended Extended Extended Extended -- Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended, windowed direct Indirect, indexed, extended, windowed direct Indirect, indexed, extended, windowed direct Indirect, indexed, extended
Internal flash program memory or external program memory (Notes 1 and 2) Internal flash special-purpose memory or external special-purpose memory (PIH vectors) (Notes 1 and 2) Internal flash program memory or external program memory (Notes 1 and 2). After reset, the first instruction is fetched from FF2080H. Internal flash special-purpose memory or external special-purpose memory (CCBs, interrupt vectors, and PTS vectors) (Notes 1 and 2) Internal flash program memory or external program memory (Notes 1 and 2) External memory or I/O (Note 1) External memory or I/O Reserved for future microcontrollers, do not access these locations. (Note 3) External memory or I/O Memory-mapped special-function registers (SFRs)
Peripheral special-function registers (SFRs)
CAN special-function registers (SFRs)
Upper register file (general-purpose register RAM)
External memory or I/O
NOTES: 1. During test ROM execution mode, the contents of pages FFH and FBH are swapped. This allows the microcontroller to enter a test ROM routine after reset. 2. Accesses to these locations go to internal flash if EA# is high or an external device if EA# is low. 3. Since the upper three address bits, A23:21, are not connected to external pins, these address locations are unique internally, but not externally. For example, addresses 200F20H, 400F20H, 600F20H appear externally on address pins A20:0 as 000F20H. 4. The IRAM_CON register determines whether accesses to these locations go to internal code/data RAM or external memory. Accesses to these locations go internal if IRAM_CON.6 = 0 and external if IRAM_CON.6 = 1.
Datasheet
21
Intel(R) 88CO196EC
Table 4.
Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller Address Map (Sheet 2 of 2)
Hex Address 000EFF 000400 0003FF 000100 0000FF 000018 000017 000000 Description Addressing Modes for Data Accesses Indirect, indexed, extended Indirect, indexed, extended, windowed direct Direct, indirect, indexed, extended Direct, indirect, indexed, extended
Internal code/data RAM or external memory (Note 4)
Upper register file (general-purpose register RAM)
Lower register file (general-purpose register RAM) Lower register file (stack pointer and CPU SFRs)
NOTES: 1. During test ROM execution mode, the contents of pages FFH and FBH are swapped. This allows the microcontroller to enter a test ROM routine after reset. 2. Accesses to these locations go to internal flash if EA# is high or an external device if EA# is low. 3. Since the upper three address bits, A23:21, are not connected to external pins, these address locations are unique internally, but not externally. For example, addresses 200F20H, 400F20H, 600F20H appear externally on address pins A20:0 as 000F20H. 4. The IRAM_CON register determines whether accesses to these locations go to internal code/data RAM or external memory. Accesses to these locations go internal if IRAM_CON.6 = 0 and external if IRAM_CON.6 = 1.
22
Datasheet
Intel(R) 88CO196EC
5.0
Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ....................................... -60C to +150C VCC Supply Voltage with Respect to VSS .......... -0.5 V to +6.0 V VPP (maximum) ..................................................................13.0 V Power Dissipation............................................................... 1.5 W NOTICE: This datasheet contains information on products being sampled or in the initial production phase of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
OPERATING CONDITIONS
TC (Case Temperature Under Bias) (note 4) ................................ Extended Temperature............. -40C to +85C Commercial Temperature......... 0C to +70C VCC (Digital Supply Voltage) ............................. 4.75 V to 5.25 V VPP (normal operation).................................................. tie to VSS VPP (Flash program/erase)..................................11.4 V to 12.6 V VREF (Analog Supply Voltage) .......................... 4.75 V to 5.25 V FXTAL1 (Input frequency for VCC = 4.75 V - 5.25 V) (Notes 1, 2, 3).................................................. 16MHz to 40MHz
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTE: 1. This device is static and should operate below 1 Hz, but has been tested only down to 16 MHz. 2. When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 6 MHz. The PLL cannot be run at frequencies lower than 24 MHz in 4X mode. 3. Assume an external clock. The maximum frequency for an external crystal oscillator is 20MHz. 4. Flash programming and erase operations only guaranteed to work from 0C to +70C.
5.1
Table 5.
DC Characteristics
DC Characteristics at VCC = 4.75 V - 5.25 V (Sheet 1 of 2)
Sym Parameter Min Typical (Note 1) Max Units Test Conditions
ICC
VCC supply current 40MHz Idle mode current 40MHz Powerdown mode current
100
130
mA
VCC = 5.25 V Device in Reset VCC = 5.25 V VCC = 5.25 V
IIDLE IPD
60 50
85
mA A
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P7.7:0, P8.7:0, P9.7:0, RESET#, NMI, CRIN, CRDCLK, ONCE#, and XTAL1. 3. The maximum injection current is not tested. The device is designed to meet this specification. 4. Pin capacitance is not tested. This value is based on design simulations.
Datasheet
23
Intel(R) 88CO196EC
Table 5.
DC Characteristics at VCC = 4.75 V - 5.25 V (Sheet 2 of 2)
Sym Parameter Min Typical (Note 1) Max Units Test Conditions XTAL1 = 40 MHz IREF A/D reference supply current Maximum injection current per port on bidirectional pins (Note 3) Input leakage current (Standard inputs except analog inputs) Input leakage current (analog inputs) Input high current (NMI only) Input low voltage (Note 2) Input high voltage (Note 2) Output low voltage (output configured as complementary) Output high voltage (output configured as complementary) Output high current in reset (on any pin except ONCE# and TMODEx#) Output low voltage in reset (on ALE) Hysteresis voltage on RESET# Pin Capacitance (any pin to VSS) (Note 4) Pull-up resistor on RESET# pin VPP Current during erase/write operation 9 700 10 95 40 VCC - 0.3 VCC - 0.7 VCC - 1.5 -30 -65 -75 -140 -280 -350 0.5 -0.5 0.7 VCC 6 mA VCC = VREF = 5.25 V Device in Reset
IINJD
-10
10
mA
ILI ILI1 IIH VIL1 VIH1
-10
10
A
VSS < VIN < VCC VSS + 100 mV < VIN < VREF - 100 mV NMI = VCC = 5.25 V
-300
300 175 0.3 VCC VCC + 0.5 0.3 0.45 1.5
nA A V V V V V V V V A A A V mV pF k mA
IOL = 200 A IOL = 3.2 mA IOL = 7 mA IOH = -200 A IOH = -3.2 mA IOH = -7 mA VOH2 = VCC - 1 V VOH2 = VCC - 2.5 V VOH2 = VCC - 4 V IOL = 15 A
VOL1
VOH1
IOH2
VOL2 VHYS CS RRST Ipph
Not tested VCC = 5.25 V VIN = 4 V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P7.7:0, P8.7:0, P9.7:0, RESET#, NMI, CRIN, CRDCLK, ONCE#, and XTAL1. 3. The maximum injection current is not tested. The device is designed to meet this specification. 4. Pin capacitance is not tested. This value is based on design simulations.
24
Datasheet
Intel(R) 88CO196EC
6.0
Table 6.
Explanation of AC Symbols
AC Timing Symbol Definitions
Character A BR C D H L Q R S W X Y Character H L V X Z High Low Valid No Longer Valid Floating (low impedance) AD15:0, A20:0 BREQ# CLKOUT AD15:0, AD7:0, RXD (SIO mode 0 input data), SDx (SSIO input data) CRBUSY# ALE/ADV# AD15:0, AD7:0, RXD (SIO mode 0 output data), SDx (SSIO output data) RD# CSx# WR#, WRH#, WRL# XTAL1, TXD (SIO clock), SCx (SSIO standard mode clock) READY Condition Signal(s)
Datasheet
25
Intel(R) 88CO196EC
6.1
AC Characteristics -- Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 7.
AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2)
Symbol FXTAL1 f Parameter Frequency on XTAL1, PLL in 1x mode (disabled) Frequency on XTAL1, PLL in 4x mode Operating frequency, f = FXTAL1; PLL in 1x mode (disabled) Operating frequency, f = 4FXTAL1; PLL in 4x mode t TAVDV TRLDV TCHDV TRHDZ TRXDX TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TQVWH TCHWH Period, t = 1/f; Address Valid to Input Data Valid RD# Low to Input Data Valid CLKOUT High to Input Data valid RD# High to Input Data Float Data Hold after RD# Inactive XTAL1 Rising Edge to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Low to ALE High ALE Low to CLKOUT High ALE Cycle Time ALE High Period Address Setup to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low to RD# High RD# High to ALE High RD# Low to Address Float ALE Low to WR# Low Output Data Stable to WR# High CLKOUT High to WR# High t - 12 t - 14 - 15 6.5 t - 10 t - 15 t - 10 t - 15 - 10 t - 10 t-5 t + 15 5 20 t - 10 - 10 - 15 4t t + 10 0 3 2t t + 15 10 15 50 Min 16 6 16 24 25 Max 40 10 40 40 62.5 3t - 40 t - 30 2t - 35 t+3 Units MHz (1, 2) MHz MHz MHz ns ns (3) ns (3) ns (4) ns ns ns (4) ns (4) ns (4) ns (4) ns (4) ns (3) ns ns ns ns ns (4) ns (3) ns (5) ns ns ns (3) ns (4)
NOTES: 1. 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be applied with an external clock source. 2. Device is static by design, but has been tested only down to 16MHz. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assumes CLKOUT is operating in divide-by-two mode (f/2). 5. Assuming back-to-back bus cycles. 6. 8-bit bus only. 7. When forcing wait states using the BUSCONx register, add 2t x n, where n = number of wait states. 8. Exceeding the maximum specification causes additional wait states. 9. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required.
26
Datasheet
Intel(R) 88CO196EC
Table 7.
AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2)
Symbol TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX TWHSH TRHSH TAVYV TCLYX TYLYH WR# Low to WR# High Output Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High AD15:8, CSx# Hold after WR# High BHE#, INST Hold after RD# High AD15:8, CSx# Hold after RD# High A20:0, CSx# Hold after WR# High A20:0, CSx# Hold after RD# High AD15:0 Valid to READY Setup READY Hold after CLKOUT Low READY Low to READY High 0 40 MHz = t-9 40 MHz = t-13 Parameter Min t - 10 t - 13 t - 15 t-4 t-9 t-5 t-5 - 0.5 0 2t - 55 2t - 45 t + 20 Max Units ns (3) ns ns ns ns (6) ns (6) ns (6) ns ns ns (7) ns (4,8,9) ns
No Upper Limit
NOTES: 1. 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be applied with an external clock source. 2. Device is static by design, but has been tested only down to 16MHz. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assumes CLKOUT is operating in divide-by-two mode (f/2). 5. Assuming back-to-back bus cycles. 6. 8-bit bus only. 7. When forcing wait states using the BUSCONx register, add 2t x n, where n = number of wait states. 8. Exceeding the maximum specification causes additional wait states. 9. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required.
Datasheet
27
Intel(R) 88CO196EC
Figure 4.
System Bus Timing Diagram (Multiplexed Bus Mode)
TCLCL t TCLLH TCHDV TRLCL TCHCL
CLKOUT
TLLCH TLHLH TLLRL TRHLH TLHLL
ALE
TRLRH TRLAZ TRHDZ
RD#
TAVLL TRLDV TLLAX TAVDV Data In TLLWL TWLWH TCHWH TWHLH TWHQX
AD15:0 (read)
Address Out
WR#
TQVWH
AD15:0 (write) BHE#, INST
Address Out
Data Out
Address Out TWHBX, TRHBX
TWHAX, TRHAX
AD15:8 A20:16 CSx#
High Address Out
Extended Address Out TWHSH, TRHSH
A3252-01
28
Datasheet
Intel(R) 88CO196EC
Figure 5.
READY Timing Diagram (Multiplexed Bus Mode)
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD# AD15:0 (read) WR#
TRLDV + 2t TAVDV + 2t Address Out TWLWH + 2t Data In
TQVWH + 2t
AD15:0 (write) BHE#, INST A20:16 CSx#
Address Out
Data Out
Extended Address Out
A3249-01
Datasheet
29
Intel(R) 88CO196EC
6.2
AC Characteristics -- Demultiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 8.
AC Characteristics, Demultiplexed Bus Mode (Sheet 1 of 2)
Symbol Parameter Frequency on XTAL1, PLL in 1x mode (disabled) FXTAL1 Frequency on XTAL1, PLL in 4x mode f Operating frequency, f = FXTAL1; PLL in 1x mode (disabled) Operating frequency, f = 2FXTAL1; PLL in 4x mode t TAVDV TRLDV TAVWL TAVRL TSLDV TCHDV TRHRL TRXDX TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TRLCL TRLRH TRHLH TWLCL TQVWH TCHWH Period, t = 1/f Address Valid to Input Data Valid RD# Low to Input Data Valid Address Valid to WR# Low Address Valid to RD# Low CSx# Low to Data Valid CLKOUT High to Input Data Valid Read High to Read Low Data Hold after RD# Inactive XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT High ALE Low ALE High to CLKOUT Low ALE Cycle Time ALE High Period RD# Low to CLKOUT Low RD# Low to RD# High RD# High to ALE Low WR# Low to CLKOUT Low Output Data Stable to WR# High CLKOUT High to WR# High t-5 0 3 2t t - 10 - 10 - 15 4t t - 10 - 15 3t - 18 t-4 - 15 3t - 25 - 11 10 t + 15 5 t + 10 5 t + 15 10 15 50 t t-8 4t - 40 2t - 35 6 16 24 25 10 40 40 62.5 4t -40 3t - 35 Min 16 Max 40 Units MHz (1,2) MHz MHz MHz ns ns (3) ns (3) ns ns ns (3) ns (4) ns ns ns (4) ns (4) ns (4) ns (4) ns (4) ns (3,5) ns ns (4) ns (3) ns (5) ns (4) ns (5) ns (4)
1. Device is static by design but has been tested only down to 16MHz. 2. 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be applied with an external clock source. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assumes CLKOUT is operating in divide-by-two mode (f/2). 5. Assuming back-to-back bus cycles. 6. When forcing wait states using the BUSCON register, add 2t x n. 7. Exceeding the maximum specification causes additional wait states. 8. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 9. 8-bit bus only.
30
Datasheet
Intel(R) 88CO196EC
Table 8.
AC Characteristics, Demultiplexed Bus Mode (Sheet 2 of 2)
Symbol TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX TAVYV TCLYX TYLYH WR# Low to WR# High Output Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High A20:0, CSx# Hold after WR# High BHE#, INST Hold after RD# High A20:0, CSx# Hold after RD# High A20:0 Valid to READY Setup READY Hold after CLKOUT Low READY Low to READY High 0 Parameter Min 3t - 18 t-2 t-5 t-5 0 t-5 0 3t - 45 2t - 36 t + 20 t + 10 Max Units ns (3) ns ns (3) ns ns ns ns ns (6) ns (7,8,9) ns
No Upper Limit
1. Device is static by design but has been tested only down to 16MHz. 2. 20MHz is the maximum input frequency when using an external crystal oscillator; however, 40MHz can be applied with an external clock source. 3. If wait states are used, add 2t x n, where n = number of wait states. 4. Assumes CLKOUT is operating in divide-by-two mode (f/2). 5. Assuming back-to-back bus cycles. 6. When forcing wait states using the BUSCON register, add 2t x n. 7. Exceeding the maximum specification causes additional wait states. 8. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 9. 8-bit bus only.
Datasheet
31
Intel(R) 88CO196EC
Figure 6.
System Bus Timing Diagram (Demultiplexed Bus Mode)
TCHCL TCLLH
TCLCL
t TCHWH
CLKOUT
TLHLH TLLCH TWHLH TRHLH TLHLL
ALE
TRHRL TAVRL TRLRH TCHDV TRLDV TAVDV TSLDV Data In TWLCL TAVWL TWLWH TWHQX TWHAX TRHAX
RD#
AD15:0 (read)
WR#
TQVWH
AD15:0 (write) BHE#, INST A20:0 CSx#
Address Out
Data Out TWHBX, TRHBX
A8733-01
32
Datasheet
Intel(R) 88CO196EC
Figure 7.
READY Timing Diagram (Demultiplexed Bus Mode)
TCLYX (max)
CLKOUT
TAVYV
TCLYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD#
TRLDV + 2t
AD15:0 (read) WR#
TAVDV + 2t Data In TWLWH + 2t
TQVWH + 2t
AD15:0 (write) BHE#, INST A20:0 CSx#
Address Out
Data Out
A3259-02
Datasheet
33
Intel(R) 88CO196EC
6.3
Deferred Bus Timing Mode
The deferred bus cycle mode (enabled by setting CCR1.5) reduces bus contention when using the Intel(R) 88CO196EC in demultiplexed mode with slow memories. As shown in Figure 8, a delay of 2t occurs in the first bus cycle following a chip-select output change or the first write cycle following a read cycle.
Figure 8.
Deferred Bus Mode Timing Diagram
CLKOUT
TLHLH + 2t TWHLH + 2t
ALE
TRHLH + 2t TAVRL + 2t
RD#
TAVDV+ 2t
AD15:0 (read) WR# AD15:0 (write) BHE#, INST A20:0 CSx#
Data In TAVWL + 2t
Data In
Data Out
Data Out
Data Out
Address Out
Valid
Valid
A3246-02
34
Datasheet
Intel(R) 88CO196EC
6.4
Table 9.
AC Characteristics -- Serial Port, Mode 0
Serial Port Timing -- Mode 0
Symbol Serial Port Clock period TXLXL SP_BAUD x002H SP_BAUD = x001H Serial Port Clock falling edge to rising edge TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ SP_BAUD x002H SP_BAUD = x001H Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float 2t + 30 0 t + 30 4t - 27 2t - 27 4t - 30 2t - 30 2t + 30 4t + 27 2t + 27 ns ns ns ns ns ns ns ns 6t 4t ns ns Parameter Min Max Units
These timings are not tested and not guaranteed.
The minimum baud-rate (SP_BAUD) register value for receptions is x002H and the minimum baud-rate (SP_BAUD) register value for transmissions is x001H.
Figure 9.
Serial Port Waveform -- Mode
TXLXL TXD TQVXH RXD RXD
0 1 2
TXLXH
3
TXHQV
4
TXHQX
5 6
TXHQZ
7
TDVXH
Valid Valid Valid
TXHDX
Valid Valid Valid Valid Valid
A5013-01
Datasheet
35
Intel(R) 88CO196EC
6.5
Table 10.
AC Characteristics -- Synchronous Serial Port
Synchronous Serial Port Timing
Symbol TCLCL TCLCH TD1DV TCLDX TDVCX TDXCX Parameter Synchronous Serial Port Clock period Synchronous Serial Port Clock falling edge to rising edge Setup time for MSB output Output data change after clock low Setup time for input data Input data hold after clock high Min 4t 2t - 10 t 0.5t 10 t+5 1.5t + 20 Max Units ns ns ns ns ns ns
Refer to the "Programming Considerations" section of chapter 9, "Synchronous Serial I/O Port" in the Intel(R) 88CO196EC CHMOS 16-Bit Microcontroller196EC User's Manual.
Figure 10.
Synchronous Serial Port
SCx (normal transfers)
1
2
3
4
5
6
7
8
TCHCL TCLCH TCHCH
STE Bit
SDx (out)
MSB
D6
D5
D4
D3
D2
D1
D0
TD1DV
SDx (in)
valid valid valid valid valid valid valid valid
TDVCX
SCx (handshaking transfers) 1 2 3 4 5 6 7
TDXCX
8
TCXDX
TCXDV
Slave Receiver Pulls SCx low
Assumes that the SSIO is configured to sample incoming data on the rising clock edge and sample outgoing data on the falling clock edge, and that the SSIO is configured to pull the clock signal low while the channel is idle.
A3233-02
36
Datasheet
Intel(R) 88CO196EC
6.6
Table 11.
AC Characteristics -- Serial Debug Unit
Serial Debug Unit Timing
Symbol TCLCL TCHCL TDVCH TCHDX TQVCH TCHQX TCHQV TCHHL Parameter Code RAM clock cycle time Code RAM clock high period Input data setup to clock high Input data hold after clock high Output data setup to clock high Output data hold after clock high Next output data valid after clock high Last clock high to CRBUSY# low Min 2t t 10 t + 10 t - 10 t - 10 t + 10 3t + 20 Max Units ns ns ns ns ns ns ns ns
Figure 11.
Serial Debug Unit
TCLCL CRDCLK TDVCH CRIN CROUT TQVCH CRBUSY#
A5335-01
TCHCL
TCHDX valid TCHQX TCHQV TCHHL valid
valid
Datasheet
37
Intel(R) 88CO196EC
6.7
A/D Sample and Conversion Times
Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. The AD_TIME register programs the A/D sample and conversion times. Use the TSAM and TCONV specifications in Table 12 and Table 14 to determine appropriate values for SAM and CONV; otherwise, erroneous conversion results may occur. When the SAM and CONV values are known, write them to the AD_TIME register. Do not write to this register while a conversion is in progress; the results are unpredictable. Use the following formulas to determine the SAM and CONV values.
TS A M x f - 2 SAM = -----------------------------8 xf-3 T CONV CONV = --------------------------------- - 1 2xB
where:
SAM CONV TSAM TCONV f B equals a number, 1 to 7, to be written to the AD_TIME register equals a number, 2 to 31, to be written to the AD_TIME register is the sample time, in sec (Table 12 and Table 14) is the conversion time, in sec (Table 12 and Table 14) is the operating frequency, in MHz is the number of bits to be converted (8 or 10)
38
Datasheet
Intel(R) 88CO196EC
6.7.1
Table 12.
AC Characteristics -- A/D Converter, 10-Bit Mode
10-bit A/D Operating Conditions
Symbol TC VCC VREF TSAM TCONV Case Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Description Min - 40 4.75 4.75 1.0 10.0 15.0 Max + 125 5.25 5.25 Units Notes 1
C
V V
s s
2 3 3
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 13.
10-Bit Mode A/D Characteristics Over Specified Operating Conditions
Parameter Typical (2) Min 1024 10 0 0.25 0.5 0.25 0.5 1.0 2.0 - 0.75 0.1 0.25 0.009 0.009 0.009 - 60 - 60 - 60 750 ANGND 3.0 100 0 300 1.2k VREF 0 0 3.0 + 0.75 1.0 Max 1024 10 3.0 Units (3) Levels Bits LSBs LSBs LSBs LSBs LSBs LSBs LSBs LSB/C LSB/C LSB/C dB dB dB W V pF nA 8 2, 4, 5 2, 4 2, 4 6 7 Notes 1 Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off-isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage
NOTES: 1. All conversions were performed with processor in idle mode. 2. Most devices will need these values at 25C, but they are not tested or guaranteed. 3. An LSB, as used here, has a value of approximately 5 mV. 4. DC to 100 KHz. 5. Multiplexer break-before-make guaranteed. 6. Resistance from device pin, through internal multiplexer, to sample capacitor. 7. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 8. 100 mV < VIN < VREF - 100 mV.
Datasheet
39
Intel(R) 88CO196EC
6.7.2
Table 14.
AC Characteristics -- A/D Converter, 8-Bit Mode
8-Bit A/D Operating Conditions
Symbol Description Min Max Units Notes 1 TC vCC vREF TSAM TCONV Case Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time - 40 4.75 4.75 1.0 8.0 12.8 + 125 5.25 5.25
C
V V
s s
2 3 3
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 15.
8-Bit Mode A/D Characteristics Over Specified Operating Conditions
Parameter Typical (2) Min Max Units (3) Notes 1 Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3.0 100 0 300 - 60 - 60 750 ANGND 1.2K VREF 0.003 0.003 0.003 - 60 LSB/C LSB/C LSB/C dB dB dB V pF nA 8 2, 4, 5 2, 4 2, 4 6 7 0.25
0.5
256 8 0 0.5 0 - 0.5 0 0
256 8 1.0
Levels Bits LSBs LSBs LSBs
1.0 + 0.5 1.0
LSBs LSBs LSBs LSBs
NOTES: 1. All conversions were performed with processor in idle mode. 2. Most parts will need these values at 25C, but they are not tested or guaranteed. 3. An LSB, as used here, has a value of approximately 5 mV. 4. DC to 100 KHz. 5. Multiplexer break-before-make guaranteed. 6. Resistance from device pin, through internal multiplexer, to sample capacitor. 7. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 8. 100 mV < VIN < VREF - 100 mV.
40
Datasheet
Intel(R) 88CO196EC
6.8
Table 16.
External Clock Drive
External Clock Drive
Symbol FXTAL1 TXTAL1 TXHXX TXLXX TXLXH TXHXL Parameter Frequency on XTAL1 (1/TXLXL), PLL in 1x mode (disabled) Frequency on XTAL1 (1/TXLXL), PLL in 4x mode Oscillator Period (TXLXL) High Time Low Time Rise Time Fall Time Min 16 6 25 0.35TXTAL1 0.35TXTAL1 Max 40
Units MHz MHz ns ns ns ns ns
10 62.5 0.65TXTAL1 0.65TXTAL1 10 10
20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source.
Figure 12.
External Clock Drive Waveforms
TXHXX 0.7 VCC + 0.5 V
XTAL1
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A2119-03
Datasheet
41
Intel(R) 88CO196EC
6.9
Figure 13.
Test Output Waveforms
AC Testing Output Waveforms
3.5 V
2.0 V Test Points 0.8 V
2.0 V 0.8 V
0.45 V
Note: AC testing inputs are driven at 3.5 V for a logic " 1" and 0.45 V for a logic " 0" . Timing measurements are made at 2.0 V for a logic " 1" and 0.8 V for a logic " 0".
A2120-04
Figure 14.
Float Waveforms During 5.0 Volt Testing
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points VOL + 0.15 V VOH - 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-03
6.10
Table 17.
Flash Memory Erase Performance
Flash Memory Erase Performance
Parameter Flash erase time Note Min Typical (see note) 2 Max 10 Unit Sec.
NOTE: Typical values are based on limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5 V; VPP= 12 V.
42
Datasheet
Intel(R) 88CO196EC
7.0
Thermal Characteristics
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information.
Table 18.
Thermal Characteristics
Package Type 132-pin PQFP with heat spreader JA 29.5 C/W JC 9 C/W
Datasheet
43

▲Up To Search▲

Price & Availability of 88CO196EC

	To Download 88CO196EC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .